1. Technical Field
The present invention relates to a substrate assembly, a method of manufacturing a substrate assembly and a method of manufacturing a chip package.
2. Description of Related Art
A photosensitive etching glass is the glass wherein only an exposed area is crystallized by exposing the glass containing a photosensitive component and photosensitization component. In the crystallized area, a dissolution speed for dissolving into acid is largely different, compared with a non-crystallized area. Accordingly, by utilizing such a nature, selective etching can be applied to the photosensitive etching glass. As a result, fine processing can be applied to the photosensitive etching glass without using mechanical processing.
Further, the photosensitive etching glass has a characteristic of a glass such that mechanical characteristics such as heat-resistance, smoothness, and rigidity, etc., are excellent, compared with a resin material. Accordingly, the photosensitive etching glass is suitably used for a substrate, etc., packaged in electronic equipment.
In recent years, higher density of an electronic circuit packaged in the equipment, is required with a progress of miniaturization of the electric equipment. In order to response to such a request, a packaging area is reduced by using an interposer interposed between a chip element such as a semiconductor element and a wiring board for electrically connecting them. When the photosensitive etching glass is utilized as the interposer, a through hole is formed on the photosensitive etching glass, and the through hole is filled with a conductive substance (for example, see patent document 1).
Further, as another method for responding to the miniaturization of the electronic equipment, a wafer level package is performed, which is configured to form external terminals, etc., in each chip element to obtain a chip package, in a stage of a wafer in which a plurality of chip elements are formed (for example, see patent documents 2 and 3). After the wafer level package is performed, the package is divided into chip element units, and each of them is packaged in the wiring board, etc. In the wafer level package, the substrate such as an interposer, etc., is bonded to the wafer, and this structure is divided individually in some cases.
Patent Document 1
    International Publication No. 2008/105496Patent Document 2    Japanese Patent Laid Open Publication No. 2004-214501Patent Document 3    Japanese Patent Laid Open Publication No. 2004-319656
When the wafer and the substrate are bonded to each other, it is necessary to bond them while securing an electric connection between the wafer and the substrate. For example, the wafer and the substrate are thermally bonded to each other, with solder and ACF (Anisotropic Conductive Film), etc., interposed between them.
Such a thermal bond is carried out at a higher temperature (for example about 150 to 300° C.) than a room temperature. Accordingly, when a thermal expansion coefficient of the wafer and a thermal expansion coefficient of the substrate are largely different from each other, there is a problem that thermally bonded wafer and substrate are warped due to a stress caused by a difference of the thermal expansion coefficients when the temperature is decreased to the room temperature after thermal bond. Particularly, when a thickness of the wafer or the substrate is decreased to achieve a higher density and lower height of the substrate, warp of the wafer or the substrate occurs remarkably.
Further, the wafer and the substrate are thermally bonded to each other in some cases by using a handling substrate before the thermal bond, for assisting a thin substrate, with the handling substrate and the substrate bonded to each other. However, in this case as well, if the thermal expansion coefficient of the handling substrate and the thermal expansion coefficient of the substrate are largely different from each other, as shown in FIG. 6, a handling substrate 100 and a substrate 300 are warped or peeled-off before cooling, thus making it difficult to perform the thermal bond between the wafer and the substrate.
In order to solve such a problem, it can be considered that the thermal expansion coefficient of the wafer or the handling substrate and the thermal expansion coefficient of the substrate are set to about the same values. However, in this case, selection of materials is limited. For example, the thermal expansion coefficient of the photosensitive etching glass is about 10 ppm/° C., and the thermal expansion coefficient of a Si wafer is about 2.6 ppm/° C., thus involving a problem that the photosensitive etching glass having a suitable characteristic as a substrate cannot be used for the above purpose of use.
Therefore, an object of the present invention is to provide a substrate assembly not allowing the warp to occur and a method of manufacturing the same, even when the substrate assembly is formed by combining substrates having largely different thermal expansion coefficients. Further, an object of the present invention is to provide a method of manufacturing a chip package in an individually divided state divided from the substrate assembly obtained by the wafer level package.
In order to achieve the above-described object, the warp of the substrate assembly is a result of a stress caused by the difference of the thermal expansion coefficients which appears as the warp, wherein the stress is inevitably generated by a temperature variation, and therefore inventors of the present invention considers it difficult to have a structure not allowing the stress to occur. Then, it is found that the warp can be suppressed by not allowing the stress to occur, but employing a structure for preventing the generated stress from appearing as the warp.
Specifically, when the substrate assembly is fabricated by combining the substrates having largely different thermal expansion coefficients, a substrate having almost the same thermal expansion coefficient as the thermal expansion coefficient of one of the substrates, is prepared. It is also found that the substrate having a large thermal expansion coefficient (or small thermal expansion coefficient) is interposed by two substrates having a small thermal expansion coefficient (or large thermal expansion coefficient), and the stress is remained inside of the substrate assembly without allowing the stress to appear as the warp due to the difference of the thermal expansion coefficients. The present invention is thus completed.